Network devices which have a multiplicity of input ports for the reception of data such as packet data, from a variety of sources commonly provide buffering of the input ports. Thus data received at a port is stored in a buffer memory temporarily until such time as it can be transmitted onwards to its intended destination. By way of example only, the device may include some system for giving data of one type or another or data from a source or group of sources priority over other data. For this purpose the network device might have a contention-resolution system, such as a csma/cd contention-resolution system wherein data from only one port at a time may be transmitted onwardly.
Modern network devices of this general character commonly include a single large memory, or possibly a set of memories which are operated as a single logical entity. The memory may be constituted by random access memory which is under the control of an appropriate processing device which may have recourse to a table of pointers which define and provide access to individual buffers within the memory. Data from any given port may be directed to a buffer by means of a respective pointer, this buffer remaining occupied until, normally under control of the processing means and a respective read pointer, the data is onwardly transmitted either directly or by way of an output buffer and the buffer is `returned`, that is to say made available for the storage of fresh data received from one or other of the input ports.
In systems of this nature, there is a significant danger that ports that are constantly busy can demand data storage in all the available memory space so that other ports which are receiving data are deprived of buffers for the storage of data received at those ports. In such circumstances data packets may be dropped, to the obvious detriment of the performance of the network, particularly in respect of traffic through non-congested ports.
It is common practice to provide some protection for the congestion of buffer memory. One example is to provide for each receiving port a respective buffer of which the operation is independent of the main common buffer memory and which acts as another stage of buffering. For example, a first-in, first-out (FIFO) memory may be provided for each port. Such a solution requires additional hardware and control for each port. Another solution is to associate in the main common memory certain groups of buffers with each port, so that a portion of the buffer memory is reserved for the use of each respective port. Such a system is more complex to control than an ordinary buffer memory and is somewhat inflexible.